1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a Bi-CMOS device having a bipolar transistor and a field effect transistor formed on the same semiconductor substrate. The present invention also relates to a method of manufacturing such a Bi-CMOS device.
2. Description of the Background Art
VLSI represented by a memory or processor tends to be made large in scale in recent years. In order to cope with such a tendency, a CMOS having characteristics of a high integration density and low power consumption has often been used. Although an operation speed of a MOS has increased with advancement of microtechnology, requirements for a higher speed are not sufficiently met presently. A bipolar device mainly of ECL is the mainstream in the field of a device operating at a high speed. However, power consumption of the bipolar device is extremely high, which places a heavy restriction on high integration.
In order to implement a device of a high speed and low power consumption, Bi-CMOS technology enabling a device having characteristics of a high integration and low power consumption of the CMOS and a high speed operation of the bipolar, as shown in FIG. 1, has been paid attention to.
FIG. 2 is a cross sectional view of a conventional Bi-CMOS. Referring to FIG. 2, an epitaxial layer Ep is formed on the surface of a silicon substrate 1. An NMOSFET, a PMOSFET, and a bipolar transistor are formed on the epitaxial layer Ep.
Description will be given of a method of manufacturing the conventional Bi-CMOS.
Referring to FIG. 3, an oxide film 2 and a nitride film 3 are formed sequentially on the main surface of silicon substrate 1 of a p type having resistivity of 10 .OMEGA.cm. Oxide film 2 and nitride film 3 are patterned to form an opening on a portion in which an N.sup.+ buried layer is to be formed. Antimony is doped into the surface of silicon substrate 1 through the opening.
Referring to FIG. 4, in a portion to which antimony is doped, antimony is diffused by annealing at a high temperature (for example, 1180.degree. C.) to form an N.sup.+ buried layer 4. At this time, removal of defects and formation of a surface oxide layer 5 of N.sup.+ buried layer 4 are simultaneously carried out.
Referring to FIGS. 3 and 4, nitride film 3 is removed to carry out ion implantation of boron. At this time, since surface oxide layer 5 is thicker than oxide film 2, surface oxide layer 5 serves as a mask of the ion implantation. Then, by carrying out annealing at a high temperature, implanted boron is diffused to form a P.sup.+ buried layer 6 in silicon substrate 1.
Referring to FIGS. 4 and 5, surface oxide layer 5 and oxide film 2 are removed.
Referring to FIG. 6, an intrinsic type epitaxial layer Ep having the thickness of approximately 1 .mu.m to 1.5 .mu.m is formed on silicon substrate 1. By oxidizing the surface of the epitaxial layer Ep, a thin oxide film 8 is formed. A nitride film is deposited on oxide film 8 (not shown). The nitride film is patterned so as to expose the surface of oxide film 8 on N.sup.+ buried layer 4 (not shown). With the nitride film used as a mask, ions of phosphorus are shallowly implanted. Then, ions of phosphorus are deeply implanted to form an N.sup.+ layer 9a. With the nitride film used as a mask, oxide film 10 is formed thick on N.sup.+ layer 9a. Then, the nitride film is removed. With oxide film 10 used as a mask, ions of boron are implanted through oxide film 8.
Referring to FIG. 7, a p well 11 is formed in the epitaxial layer Ep in which boron is implanted by driving (thermal diffusion) at 1000.degree. C. for 150 to 250 minutes, and an n well 9 is formed by diffusion of N.sup.+ layer 9a.
Referring to FIGS. 6 and 7, after removing thin oxide film 8 and thick oxide film 10, an oxide film 12 is formed thin (10 nm). Polysilicon 13 is deposited 50 nm on oxide film 12. A nitride film 14 is further deposited thick (240 nm) thereon. Oxide film 12, polysilicon 13, and nitride film 14 are patterned so as to be left only on active regions A.sub.1, A.sub.2, A.sub.3, A.sub.4 with lithography technology. With the obtained pattern used as a mask, ions and boron are implanted into the surface of the substrate for channel cut.
Referring to FIGS. 7 and 8, with nitride film 12 used as a mask, the surface of the substrate is oxidized, whereby a field oxide film 15 of the thickness of approximately 800 nm is formed on the surface of the substrate. After removing oxide film 14, polysilicon 13, and nitride film 12, an oxide film 16 is formed thin (20 nm or less) on active regions A.sub.1, A.sub.2, A.sub.3, A.sub.4. Resist 17 having an opening on active region A.sub.4 is formed on the substrate. With resist 17 used as a mask, ions of phosphorus are implanted into active region A.sub.4 shallowly, and then, deeply.
Referring to FIGS. 8 and 9, by removing resist 17 and carrying out annealing at a high temperature, a drawing-out portion 18 of a collector is formed in active region A.sub.4. Referring to FIG. 10, resist 19 having an opening on active region A.sub.3 is formed on the substrate. With resist 19 used as a mask, ions of boron are implanted into active region A.sub.3.
Referring to FIGS. 10 and 11, by carrying out annealing at a high temperature after removal of resist 19, a P-type base region 20 is formed on the surface of active region A.sub.3.
Ions are implanted for adjustment of a threshold value into a region in which a MOS transistor is to be formed, that is, active regions A.sub.1, A.sub.2.
Referring to FIGS. 11 and 12, after removing oxide film 16 on active regions A.sub.1, A.sub.2, A.sub.3, A.sub.4, a gate oxide film 21 of the thickness of 20 nm is formed. Polysilicon 22 is further deposited thereon.
Referring to FIGS. 12 and 13, by patterning polysilicon 22, a gate electrode 24 is formed on active region A.sub.1, and a gate electrode 25 is formed on active region A.sub.2.
Referring to FIG. 14, such resist pattern 27 as covers part of active region A.sub.1, part of active region A.sub.2, and all of active region A.sub.3 is formed on the substrate. With gate electrode 24 and resist 27 used as a mask, ions of phosphorus are implanted into the surface of the substrate, whereby a source/drain low concentration impurity region (an N.sup.- -type LDD (lightly doped drain) region) 28 is formed, and a low concentration impurity region 281 is formed in the surface of active region A.sub.2. Then, resist pattern 27 is removed.
Referring to FIG. 15, a TEOS (tetraethyl orthosilicate) film 29 of the thickness of 300 nm is formed on the entire surface of silicon substrate 1.
Referring to FIGS. 15 and 16, by anisotropically etching TEOS film 29, sidewall spacers 29a, 29b are formed on sidewalls of gate electrodes 24, 25, respectively.
Referring to FIG. 17, resist pattern 30 having the same pattern as that used in the step of FIG. 14 is formed on silicon substrate 1. Referring to FIGS. 17 and 18, with resist pattern 30 used as a mask, ion implantation 400 into the surface of silicon substrate 1 is carried out to form a source/drain high concentration region 31 and an N-type common electrode 32. Then, resist pattern 30 is removed.
Referring to FIG. 19, a resist pattern 33 as shown in the figure is formed on silicon substrate 1 having openings on part of active region A.sub.1, part of active region A.sub.2, and part of active region A.sub.3. Referring to FIGS. 19 and 20, with resist pattern 33 used as a mask, ions of boron are implanted, whereby a source/drain region 34, a P-type common electrode 35, and an external base region 46 are formed. Then, resist pattern 33 is removed.
Referring to FIG. 21, a TEOS film 36 of the thickness of 200 nm is deposited on silicon substrate 1. By using lithography technology, an opening 36a for exposing a base region 20 in active region A.sub.3 is formed in TEOS film 36. Referring to FIG. 22, polysilicon 37 is deposited on the entire surface of silicon substrate 1 to fill opening 36a. Ions of As are implanted into polysilicon 37. By implanting ions of As into polysilicon 37, an emitter region 48 is formed in the surface of base region 20.
Referring to FIGS. 22 and 23, by patterning polysilicon 37, an emitter electrode 38 is formed. A protective insulating film 39 is formed on silicon substrate 1 so as to cover gate electrode 24, base electrode 25, and emitter electrode 38. A contact hole for electrical connection is formed in protective insulating film 39. An electrode interconnection 40 is electrically connected to the NMOS, the PMOS, and the bipolar transistor through the contact hole.
The conventional Bi-CMOS device was formed by a method as described above. Therefore, referring to FIGS. 15 and 16, when TEOS film 29 was etched to form sidewall spacers 29a, 29b on sidewalls of gate electrode 24, 25, active regions A.sub.3, A.sub.4 in which the bipolar transistor is to be formed were subjected to reactive ion etching, causing active regions A.sub.3, A.sub.4 to be damaged.
As a result, referring to FIG. 24, a base current (I.sub.B) became large on the side of the low V.sub.BE (base-emitter voltage) (refer to the dotted line (2)). In FIG. 24, comparison of the conventional example with the present invention is illustrated (refer to the curve (1)).
In the bipolar transistor, a current amplification factor h.sub.FE is given by EQU h.sub.FE =I.sub.C /I.sub.B
In the bipolar transistor, it is desired that the current amplification factor (h.sub.FE) is large. However, when the base current becomes large on the side of the low V.sub.BE as shown in FIG. 24, the current amplification factor becomes small, which in turn deteriorates characteristics of the bipolar transistor.